The present invention relates to semiconductor devices and structures for mounting the semiconductor devices and more particular, to a semiconductor device having a stress relaxation structure and a method for manufacturing the semiconductor device.
In order to secure the reliability of connection between a semiconductor device and a substrate for mounting the semiconductor device thereon, a layer for relaxing a stress induced between the semiconductor device and substrate is formed therebetween.
For example, JP-A-11-54649 (referred to as the first known example, hereinafter) discloses a semiconductor device wherein a layer having a low elastic modulus is formed on a semiconductor substrate and a plurality of metallic balls are formed on the low elastic modulus layer as external connection terminals.
Also disclosed in JP-A-2-272737 (referred to as the second known example, hereinafter) is a projected electrode structure of semiconductor which includes an aluminum pad electrode for a semiconductor microchip, a protective film formed on the semiconductor element except for part of the aluminum pad electrode, a projection formed on the protective film, a connection pattern provided so as to cover the pad electrode and the surface of the projection, and an insulating layer provided on the protective film and connection pattern so as to expose at least the top of the projected electrode having the projection and pattern.
Further disclosed in JP-A-7-45665 (referred to as the third known example, hereinafter) is a circuit board wherein, in order to relax a stress induced resulting from a difference in thermal expansion coefficient between the circuit board and a semiconductor microchip, a layer made of a material having a small elastic modulus (low elastic modulus resin layer) is provided under a connection electrode layer of the circuit board having a projected electrode of the semiconductor element joined thereto.
JP-A-2000-353763 (referred to as the fourth known example, hereinafter) also discloses a projected electrode which includes a rewiring layer formed on a semiconductor wafer, a Cu plated layer provided on the wafer for connection with the rewiring layer, a resin film layer of a trapezoidal shape formed on the Cu plated layer, and a metallic layer formed on the film layer for connection with the plated layer.